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Merge changes I46c81dba,If1f40e9c,I652eaaa5

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* changes:
  stagefright aacenc: Use QDADD/QDSUB instructions
  stagefright aacenc: Remove useless inline asm for simple right shift
  stagefright aacenc: Use ARMv6 SSAT instruction
This commit is contained in:
Jean-Baptiste Queru
2012-02-29 14:24:52 -08:00
committed by android code review
parent 69aae36e90 2757ab24b8
commit 704131cb7e
3 changed files with 43 additions and 14 deletions
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2
media/libstagefright/codecs/aacenc/Android.mk
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@@ -79,7 +79,7 @@ LOCAL_C_INCLUDES += $(LOCAL_PATH)/src/asm/ARMV5E
endif
ifeq ($(VOTT), v7)
LOCAL_CFLAGS += -DARMV5E -DARMV7Neon -DARM_INASM -DARMV5_INASM
LOCAL_CFLAGS += -DARMV5E -DARMV7Neon -DARM_INASM -DARMV5_INASM -DARMV6_INASM
LOCAL_C_INCLUDES += $(LOCAL_PATH)/src/asm/ARMV5E
LOCAL_C_INCLUDES += $(LOCAL_PATH)/src/asm/ARMV7
endif

48
media/libstagefright/codecs/aacenc/basic_op/basic_op.h
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@@ -227,13 +227,7 @@ Word32 L_shr_r (Word32 L_var1, Word16 var2);
#if ARMV4_INASM
__inline Word32 ASM_L_shr(Word32 L_var1, Word16 var2)
{
Word32 result;
asm (
"MOV %[result], %[L_var1], ASR %[var2] \n"
:[result]"=r"(result)
:[L_var1]"r"(L_var1), [var2]"r"(var2)
);
return result;
return L_var1 >> var2;
}
__inline Word32 ASM_L_shl(Word32 L_var1, Word16 var2)
@@ -264,6 +258,18 @@ __inline Word32 ASM_shr(Word32 L_var1, Word16 var2)
__inline Word32 ASM_shl(Word32 L_var1, Word16 var2)
{
#if ARMV6_SAT
Word32 result;
asm (
"CMP %[var2], #16\n"
"MOVLT %[result], %[L_var1], ASL %[var2]\n"
"MOVGE %[result], %[L_var1], ASL #16\n"
"SSAT %[result], #16, %[result]\n"
:[result]"=r"(result)
:[L_var1]"r"(L_var1), [var2]"r"(var2)
);
return result;
#else
Word32 result;
Word32 tmp;
asm (
@@ -277,6 +283,7 @@ __inline Word32 ASM_shl(Word32 L_var1, Word16 var2)
:[L_var1]"r"(L_var1), [var2]"r"(var2), [mask]"r"(0x7fff)
);
return result;
#endif
}
#endif
@@ -288,7 +295,15 @@ __inline Word32 ASM_shl(Word32 L_var1, Word16 var2)
#if (SATRUATE_IS_INLINE)
__inline Word16 saturate(Word32 L_var1)
{
#if ARMV5TE_SAT
#if ARMV6_SAT
Word16 result;
asm (
"SSAT %[result], #16, %[L_var1]"
: [result]"=r"(result)
: [L_var1]"r"(L_var1)
);
return result;
#elif ARMV5TE_SAT
Word16 result;
Word32 tmp;
asm volatile (
@@ -445,8 +460,7 @@ __inline Word32 L_msu (Word32 L_var3, Word16 var1, Word16 var2)
Word32 result;
asm (
"SMULBB %[result], %[var1], %[var2] \n"
"QADD %[result], %[result], %[result] \n"
"QSUB %[result], %[L_var3], %[result]\n"
"QDSUB %[result], %[L_var3], %[result]\n"
:[result]"=&r"(result)
:[L_var3]"r"(L_var3), [var1]"r"(var1), [var2]"r"(var2)
);
@@ -671,7 +685,16 @@ __inline Word16 div_s (Word16 var1, Word16 var2)
#if (MULT_IS_INLINE)
__inline Word16 mult (Word16 var1, Word16 var2)
{
#if ARMV5TE_MULT
#if ARMV5TE_MULT && ARMV6_SAT
Word32 result;
asm (
"SMULBB %[result], %[var1], %[var2] \n"
"SSAT %[result], #16, %[result], ASR #15 \n"
:[result]"=r"(result)
:[var1]"r"(var1), [var2]"r"(var2)
);
return result;
#elif ARMV5TE_MULT
Word32 result, tmp;
asm (
"SMULBB %[tmp], %[var1], %[var2] \n"
@@ -990,8 +1013,7 @@ __inline Word32 L_mac (Word32 L_var3, Word16 var1, Word16 var2)
Word32 result;
asm (
"SMULBB %[result], %[var1], %[var2]\n"
"QADD %[result], %[result], %[result]\n"
"QADD %[result], %[result], %[L_var3]\n"
"QDADD %[result], %[L_var3], %[result]\n"
:[result]"=&r"(result)
: [L_var3]"r"(L_var3), [var1]"r"(var1), [var2]"r"(var2)
);

7
media/libstagefright/codecs/aacenc/basic_op/typedefs.h
View File

@@ -128,6 +128,13 @@ typedef unsigned __int64 UWord64;
#define ARMV5TE_NORM_L 1
#define ARMV5TE_L_MPY_LS 1
#endif
#if ARMV6_INASM
#undef ARMV5TE_ADD
#define ARMV5TE_ADD 0
#undef ARMV5TE_SUB
#define ARMV5TE_SUB 0
#define ARMV6_SAT 1
#endif
//basic operation functions optimization flags
#define SATRUATE_IS_INLINE 1 //define saturate as inline function