diff --git a/arch/arm64/boot/dts/19721/atoll.dtsi b/arch/arm64/boot/dts/19721/atoll.dtsi
index c75bbd2db567..e65c76d1f7b0 100644
--- a/arch/arm64/boot/dts/19721/atoll.dtsi
+++ b/arch/arm64/boot/dts/19721/atoll.dtsi
@@ -697,7 +697,7 @@
 	};
 
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mitigations=off kpti=0 audit=0 nowhere cgroup_disable=memory dk=balanced";
 	};
 
 	soc: soc { };
@@ -841,6 +841,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU0>;
+		status = "disabled";
 	};
 
 	jtag_mm1: jtagmm@7140000 {
@@ -852,6 +853,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU1>;
+		status = "disabled";
 	};
 
 	jtag_mm2: jtagmm@7240000 {
@@ -863,6 +865,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU2>;
+		status = "disabled";
 	};
 
 	jtag_mm3: jtagmm@7340000 {
@@ -874,6 +877,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU3>;
+		status = "disabled";
 	};
 
 	jtag_mm4: jtagmm@7440000 {
@@ -885,6 +889,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU4>;
+		status = "disabled";
 	};
 
 	jtag_mm5: jtagmm@7540000 {
@@ -896,6 +901,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU5>;
+		status = "disabled";
 	};
 
 	jtag_mm6: jtagmm@7640000 {
@@ -907,6 +913,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU6>;
+		status = "disabled";
 	};
 
 	jtag_mm7: jtagmm@7740000 {
@@ -918,6 +925,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU7>;
+		status = "disabled";
 	};
 
 	qcom,msm-imem@146aa000 {
@@ -1559,7 +1567,7 @@
 	};
     //#endif /* FEATURE_OPPO_NV_BACKUP */
 	//#endif /* VENDOR_EDIT */
-	
+
 	pil_modem: qcom,mss@4080000 {
 		compatible = "qcom,pil-tz-generic";
 		reg = <0x4080000 0x100>;
@@ -2031,6 +2039,7 @@
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
+		status = "disabled";
 
 		rpmh {
 			qcom,dump-size = <0x2000000>;
@@ -2355,7 +2364,7 @@
 
 				msm_cdsp_rm: qcom,msm_cdsp_rm {
 					compatible = "qcom,msm-cdsp-rm";
-					qcom,qos-latency-us = <44>;
+					qcom,qos-latency-us = <30>;
 					qcom,qos-maxhold-ms = <20>;
 					qcom,compute-cx-limit-en;
 					qcom,compute-priority-mode = <2>;
@@ -3265,10 +3274,10 @@
 		qcom,target-dev = <&cpu0_cpu_l3_lat>;
 		qcom,cachemiss-ev = <0x17>;
 		qcom,core-dev-table =
-			<  768000  300000000 >,
-			< 1017600  556800000 >,
-			< 1248000  806400000 >,
-			< 1516800  940800000 >,
+			<  768000  556800000 >,
+			< 1017600  806400000 >,
+			< 1248000  940800000 >,
+			< 1516800 1209600000 >,
 			< 1804800 1401000000 >;
 	};
 
@@ -3285,11 +3294,11 @@
 		qcom,target-dev = <&cpu6_cpu_l3_lat>;
 		qcom,cachemiss-ev = <0x17>;
 		qcom,core-dev-table =
-			< 1113600  556800000 >,
-			< 1267200  806400000 >,
-			< 1555200  940800000 >,
-			< 1708800 1209600000 >,
-			< 1900800 1401000000 >,
+			< 1113600  806400000 >,
+			< 1267200  940800000 >,
+			< 1555200 1209600000 >,
+			< 1708800 1401000000 >,
+			< 1900800 1459000000 >,
 			< 2400000 1459000000 >;
 	};
 
@@ -3357,11 +3366,11 @@
 		qcom,target-dev = <&cpu0_llcc_ddr_lat>;
 		qcom,cachemiss-ev = <0x1000>;
 		qcom,core-dev-table =
-			<  768000 MHZ_TO_MBPS( 300, 4) >,
-			< 1017600 MHZ_TO_MBPS( 451, 4) >,
-			< 1248000 MHZ_TO_MBPS( 547, 4) >,
-			< 1516800 MHZ_TO_MBPS( 768, 4) >,
-			< 1804800 MHZ_TO_MBPS(1017, 4) >;
+			<  768000 MHZ_TO_MBPS( 547, 4) >,
+			< 1017600 MHZ_TO_MBPS( 768, 4) >,
+			< 1248000 MHZ_TO_MBPS(1017, 4) >,
+			< 1516800 MHZ_TO_MBPS(1353, 4) >,
+			< 1804800 MHZ_TO_MBPS(1555, 4) >;
 	};
 
 	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
@@ -3379,8 +3388,8 @@
 		qcom,target-dev = <&cpu6_llcc_ddr_lat>;
 		qcom,cachemiss-ev = <0x1000>;
 		qcom,core-dev-table =
-			< 1113600 MHZ_TO_MBPS( 547, 4) >,
-			< 1267200 MHZ_TO_MBPS(1017, 4) >,
+			< 1113600 MHZ_TO_MBPS(1017, 4) >,
+			< 1267200 MHZ_TO_MBPS(1353, 4) >,
 			< 1708800 MHZ_TO_MBPS(1555, 4) >,
 			< 2208000 MHZ_TO_MBPS(1804, 4) >,
 			< 2400000 MHZ_TO_MBPS(2133, 4) >;
@@ -3400,10 +3409,10 @@
 		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
 		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
 		qcom,core-dev-table =
-			<  768000 MHZ_TO_MBPS( 300, 4) >,
-			< 1248000 MHZ_TO_MBPS( 451, 4) >,
-			< 1516800 MHZ_TO_MBPS( 547, 4) >,
-			< 1804800 MHZ_TO_MBPS( 768, 4) >;
+			<  768000 MHZ_TO_MBPS( 547, 4) >,
+			< 1248000 MHZ_TO_MBPS(1017, 4) >,
+			< 1516800 MHZ_TO_MBPS(1353, 4) >,
+			< 1804800 MHZ_TO_MBPS(1555, 4) >;
 	};
 
 	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
@@ -3420,9 +3429,9 @@
 		qcom,cpulist = <&CPU6 &CPU7>;
 		qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
 		qcom,core-dev-table =
-			< 1267200 MHZ_TO_MBPS( 547, 4) >,
-			< 1555200 MHZ_TO_MBPS( 768, 4) >,
-			< 1708800 MHZ_TO_MBPS(1017, 4) >,
+			< 1267200 MHZ_TO_MBPS( 768, 4) >,
+			< 1555200 MHZ_TO_MBPS(1017, 4) >,
+			< 1708800 MHZ_TO_MBPS(1353, 4) >,
 			< 1900800 MHZ_TO_MBPS(1555, 4) >,
 			< 2208000 MHZ_TO_MBPS(1804, 4) >,
 			< 2400000 MHZ_TO_MBPS(2133, 4) >;
@@ -3967,8 +3976,8 @@
 
 			qcom,speed-bin = <159>;
 
-			qcom,initial-pwrlevel = <5>;
-			qcom,ca-target-pwrlevel = <4>;
+			qcom,initial-pwrlevel = <6>;
+			qcom,ca-target-pwrlevel = <5>;
 
 			/* NOM_L1 */
 			qcom,gpu-pwrlevel@0 {
@@ -4024,9 +4033,18 @@
 				qcom,bus-max = <7>;
 			};
 
-			/* XO */
+			/* MIN SVS */
 			qcom,gpu-pwrlevel@6 {
 				reg = <6>;
+				qcom,gpu-freq = <180000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <5>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <0>;
 				qcom,bus-freq = <0>;
 				qcom,bus-min = <0>;
diff --git a/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-boe-fhd-plus-video.dtsi b/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-boe-fhd-plus-video.dtsi
index dbe91227f5b5..b376a6646d08 100644
--- a/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-boe-fhd-plus-video.dtsi
+++ b/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-boe-fhd-plus-video.dtsi
@@ -11,281 +11,296 @@
  */
 
 &mdss_mdp {
-	dsi_nt36672c_boe_video: qcom,mdss_dsi_nt36672c_boe_video {
-		qcom,mdss-dsi-panel-name =
-			"nt36672c fhd plus video mode dsi panel";
-		qcom,mdss-dsi-panel-type = "dsi_video_mode";
-		qcom,mdss-dsi-virtual-channel-id = <0>;
-		qcom,mdss-dsi-stream = <0>;
-		qcom,mdss-dsi-bpp = <24>;
-		qcom,mdss-dsi-underflow-color = <0xff>;
-		qcom,mdss-dsi-border-color = <0>;
-		qcom,mdss-dsi-traffic-mode = "burst_mode";
-		qcom,mdss-dsi-bllp-eof-power-mode;
-		qcom,mdss-dsi-bllp-power-mode;
-		qcom,mdss-dsi-lane-0-state;
-		qcom,mdss-dsi-lane-1-state;
-		qcom,mdss-dsi-lane-2-state;
-		qcom,mdss-dsi-dma-trigger = "trigger_sw";
-		qcom,mdss-dsi-mdp-trigger = "none";
-		qcom,mdss-dsi-reset-sequence = <1 10>, <0 3>, <1 0>;
-		qcom,mdss-pan-physical-width-dimension = <69>;
-		qcom,mdss-pan-physical-height-dimension = <152>;
-		qcom,mdss-dsi-dma-schedule-line = <5>;
+    dsi_nt36672c_boe_video: qcom,mdss_dsi_nt36672c_boe_video {
+        qcom,mdss-dsi-panel-name = "nt36672c fhd plus video mode dsi panel";
+        qcom,mdss-dsi-panel-type = "dsi_video_mode";
+        qcom,mdss-dsi-virtual-channel-id = <0>;
+        qcom,mdss-dsi-stream = <0>;
+        qcom,mdss-dsi-bpp = <24>;
+        qcom,mdss-dsi-underflow-color = <0xff>;
+        qcom,mdss-dsi-border-color = <0>;
+        qcom,mdss-dsi-traffic-mode = "burst_mode";
+        qcom,mdss-dsi-bllp-eof-power-mode;
+        qcom,mdss-dsi-bllp-power-mode;
 
-		qcom,mdss-dsi-lp11-init;
-		qcom,dsi-supported-dfps-list = <60 90 45>;
-		qcom,mdss-dsi-pan-enable-dynamic-fps;
-		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+        /* Lane Configuration */
+        qcom,mdss-dsi-lane-0-state;
+        qcom,mdss-dsi-lane-1-state;
+        qcom,mdss-dsi-lane-2-state;
 
-		qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
-		qcom,platform-te-gpio = <&tlmm 10 0>;
-		qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+        /* Triggers */
+        qcom,mdss-dsi-dma-trigger = "trigger_sw";
+        qcom,mdss-dsi-mdp-trigger = "none";
+        qcom,mdss-dsi-reset-sequence = <1 10>, <0 3>, <1 0>;
 
-		oplus,is_19696_lcd;
-		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
-		qcom,mdss-dsi-bl-min-level = <1>;
-		qcom,mdss-dsi-bl-max-level = <4095>;
-                qcom,mdss-dsi-bl-normal-max-level = <2047>;
-		qcom,mdss-brightness-max-level =<2047>;
-		qcom,mdss-dsi-bl-default-level = <1024>;
-		oppo,dsi-brightness-remapping = <1    1>,
-							<2    18>,
-							<20   44>,
-							<50   58>,
-							<121  84>,
-							<200  118>,
-							<277  152>,
-							<355  190>,
-							<452  242>,
-							<605  348>,
-							<803  528>,
-							<1024 786>,
-							<1224 1116>,
-							<1425 1570>,
-							<1625 2170>,
-							<1823 2962>,
-							<2047 4095>;
+        /* Dimensions */
+        qcom,mdss-pan-physical-width-dimension = <69>;
+        qcom,mdss-pan-physical-height-dimension = <152>;
+        qcom,mdss-dsi-dma-schedule-line = <5>;
 
-		qcom,mdss-dsi-panel-hdr-enabled;
-		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
-		       16000 13250 34500 7500 3000>;
-		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
-		qcom,mdss-dsi-panel-blackness-level = <1023>;
-		qcom,panel-cphy-mode;
-		oppo,bl_interpolate_nosub;
-		oppo,mdss-dsi-vendor-name = "nt36672c";
-		oppo,mdss-dsi-manufacture = "boe vdo mode";
+        /* C-PHY & Init */
+        qcom,panel-cphy-mode;
+        qcom,mdss-dsi-lp11-init;
 
-		qcom,mdss-dsi-display-timings {
-			timing@0{
-				qcom,mdss-dsi-panel-width = <1080>;
-				qcom,mdss-dsi-panel-height = <2400>;
-				qcom,mdss-dsi-h-front-porch = <202>;
-				qcom,mdss-dsi-h-back-porch = <56>;
-				qcom,mdss-dsi-h-pulse-width = <12>;
-				qcom,mdss-dsi-h-sync-skew = <0>;
-				qcom,mdss-dsi-v-back-porch = <10>;
-				qcom,mdss-dsi-v-front-porch = <1291>;
-				qcom,mdss-dsi-v-pulse-width = <10>;
-				qcom,mdss-dsi-panel-framerate = <60>;
-				qcom,mdss-dsi-pre-on-command=[
-						29 01 00 00 00 00 02 FF C0   /*modified for VDD_TP power*/
-						29 01 00 00 0A 00 02 48 1F
-						29 01 00 00 00 00 02 FF C0
-						29 01 00 00 00 00 02 4B 0E];
-				qcom,mdss-dsi-on-command = [
-						29 01 00 00 00 00 02 FF 10
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 B0 10
-						29 01 00 00 00 00 02 C0 00       /*VESA off for C-PHY*/
-						29 01 00 00 00 00 03 C2 1B A0
+        /* FPS Configuration - Removed 45Hz as no cmd logic exists for it */
+        qcom,dsi-supported-dfps-list = <60 90>;
+        qcom,mdss-dsi-pan-enable-dynamic-fps;
+        qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
 
-						29 01 00 00 00 00 02 FF 25
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 18 20     /*60hz :21 ; 90hz:20*/
+        /* Power & GPIO */
+        qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+        qcom,platform-te-gpio = <&tlmm 10 0>;
+        qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
 
-						15 01 00 00 00 00 02 FF 2A  /*for switch 60hz TP*/
-						15 01 00 00 00 00 02 FB 01
-						15 01 00 00 00 00 02 27 80
-						15 01 00 00 00 00 02 28 FD
+        /* Backlight & Brightness */
+        oplus,is_19696_lcd;
+        qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+        qcom,mdss-dsi-bl-min-level = <1>;
+        qcom,mdss-dsi-bl-max-level = <4095>;
+        qcom,mdss-dsi-bl-normal-max-level = <2047>;
+        qcom,mdss-brightness-max-level = <2047>;
+        qcom,mdss-dsi-bl-default-level = <1024>;
 
-						/*#ifdef ODM_LQ_EDIT*/
-						/*qujiong@ODM_LQ@BSP.touch,2019/10/30,modified for TP self-test*/
-						29 01 00 00 00 00 02 FF F0
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 5A 00
-						29 01 00 00 00 00 02 A0 08
-						29 01 00 00 00 00 02 FF D0
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 09 AD
-						/*endif ODM_LQ_EDIT*/
+        oppo,dsi-brightness-remapping = <1    1>,
+                            <2    18>,
+                            <20   44>,
+                            <50   58>,
+                            <121  84>,
+                            <200  118>,
+                            <277  152>,
+                            <355  190>,
+                            <452  242>,
+                            <605  348>,
+                            <803  528>,
+                            <1024 786>,
+                            <1224 1116>,
+                            <1425 1570>,
+                            <1625 2170>,
+                            <1823 2962>,
+                            <2047 4095>;
 
-						/*#ifdef ODM_LQ_EDIT*/
-						/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
-						15 01 00 00 00 00 02 FF 10
-						15 01 00 00 00 00 02 FB 01
-						15 01 00 00 00 00 02 51 FF   /*keep pwm high when cabc off*/
-						15 01 00 00 00 00 02 53 24
-						15 01 00 00 00 00 02 FF 23
-						15 01 00 00 00 00 02 FB 01
+        /* HDR */
+        qcom,mdss-dsi-panel-hdr-enabled;
+        qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+               16000 13250 34500 7500 3000>;
+        qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+        qcom,mdss-dsi-panel-blackness-level = <1023>;
 
-						15 01 00 00 00 00 02 0A 00
-						15 01 00 00 00 00 02 0B 00
-						15 01 00 00 00 00 02 0C 00
-						15 01 00 00 00 00 02 0D 00
+        /* Vendor Info */
+        oppo,bl_interpolate_nosub;
+        oppo,mdss-dsi-vendor-name = "nt36672c";
+        oppo,mdss-dsi-manufacture = "boe vdo mode";
 
-						15 01 00 00 00 00 02 11 01
-						15 01 00 00 00 00 02 12 95
-						15 01 00 00 00 00 02 15 68
-						15 01 00 00 00 00 02 16 0B
-						15 01 00 00 00 00 02 6F 00
-						15 01 00 00 00 00 02 70 00
-						15 01 00 00 00 00 02 71 00
-						15 01 00 00 00 00 02 A0 11
-						15 01 00 00 00 00 02 FF  F0
-						15 01 00 00 00 00 02 FB 01
-						15 01 00 00 00 00 02 D2 52
-						/*#endif ODM_LQ_EDIT*/
+        /* ESD Check / Status (Merged from split node) */
+        qcom,esd-check-enabled;
+        qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+        qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 00];
+        qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; /* Keep LP for stable read */
+        qcom,mdss-dsi-panel-status-value = <0x9C>;
+        qcom,mdss-dsi-panel-on-check-value = <0x9C>;
+        qcom,mdss-dsi-panel-status-read-length = <1>;
+        qcom,mdss-dsi-panel-max-error-count = <3>;
 
-						29 01 00 00 00 00 02 FF 24
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 E3 02
-						29 01 00 00 00 00 02 FF D0
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 53 22
-						29 01 00 00 00 00 02 54 02
+        /* Clocks */
+        qcom,mdss-dsi-t-clk-post = <0x00>;
+        qcom,mdss-dsi-t-clk-pre = <0x00>;
 
-						29 01 00 00 00 00 02 FF 23
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 07 20
-						29 01 00 00 00 00 02 08 07
-						29 01 00 00 00 00 02 09 04
+        qcom,mdss-dsi-display-timings {
+            timing@0 {
+                qcom,mdss-dsi-panel-width = <1080>;
+                qcom,mdss-dsi-panel-height = <2400>;
+                qcom,mdss-dsi-h-front-porch = <202>;
+                qcom,mdss-dsi-h-back-porch = <56>;
+                qcom,mdss-dsi-h-pulse-width = <12>;
+                qcom,mdss-dsi-h-sync-skew = <0>;
+                qcom,mdss-dsi-v-back-porch = <10>;
+                qcom,mdss-dsi-v-front-porch = <1291>;
+                qcom,mdss-dsi-v-pulse-width = <10>;
+                qcom,mdss-dsi-panel-framerate = <60>;
 
-						29 01 00 00 00 00 02 FF 10
-						29 01 00 00 00 00 02 35 00
-						05 01 00 00 46 00 02 11 00
-						05 01 00 00 1E 00 02 29 00
-					];
-				qcom,mdss-dsi-off-command =[
-					29 01 00 00 00 00 02 FF 10
-					29 01 00 00 00 00 02 FB 01
-					05 01 00 00 14 00 02 28 00
-					05 01 00 00 78 00 02 10 00
-					];
-				/*#ifdef ODM_LQ_EDIT*/
-				/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
-				qcom,mdss-dsi-cabc-off-command = [
-					15 01 00 00 00 00 02 FF 10
-					15 01 00 00 00 00 02 55 00
-					];
-				qcom,mdss-dsi-cabc-ui-command = [
-					15 01 00 00 00 00 02 FF 23
-					15 00 00 00 00 00 02 FB 01
-					/*UI_PWM DUTY*/
-					15 01 00 00 00 00 02 30 FF
-					15 00 00 00 00 00 02 31 FC
-					15 00 00 00 00 00 02 32 F8
-					15 00 00 00 00 00 02 33 F4
-					15 00 00 00 00 00 02 34 F3
-					15 00 00 00 00 00 02 35 F3
-					15 00 00 00 00 00 02 36 F3
-					15 00 00 00 00 00 02 37 F2
-					15 00 00 00 00 00 02 38 F1
-					15 00 00 00 00 00 02 39 F0
-					15 01 00 00 00 00 02 3A EE
-					15 00 00 00 00 00 02 3B EC
-					15 00 00 00 00 00 02 3D EA
-					15 00 00 00 00 00 02 3F E8
-					15 00 00 00 00 00 02 40 E6
-					15 00 00 00 10 00 02 41 E4
-					15 01 00 00 00 00 02 FF 10
-					15 00 00 00 00 00 02 FB 01
-					15 00 00 00 00 00 02 51 FF
-					15 00 00 00 00 00 02 53 2C
-					15 01 00 00 00 00 02 55 01   /*mode switch*/
-					];
-				qcom,mdss-dsi-cabc-still-image-command = [
-					15 01 00 00 00 00 02 FF 23
-					15 00 00 00 00 00 02 FB 01
-					/*Still_PWM DUTY*/
-					15 01 00 00 00 00 02 45 E7
-					15 00 00 00 00 00 02 46 E0
-					15 00 00 00 00 00 02 47 D8
-					15 00 00 00 00 00 02 48 CE
-					15 00 00 00 00 00 02 49 CD
-					15 00 00 00 00 00 02 4A CC
-					15 00 00 00 00 00 02 4B CA
-					15 00 00 00 00 00 02 4C C4
-					15 00 00 00 00 00 02 4D C0
-					15 00 00 00 00 00 02 4E BF
-					15 01 00 00 00 00 02 4F BF
-					15 00 00 00 00 00 02 50 BF
-					15 00 00 00 00 00 02 51 BF
-					15 00 00 00 00 00 02 52 BF
-					15 00 00 00 00 00 02 53 BF
-					15 00 00 00 00 00 02 54 BE
-					15 01 00 00 00 00 02 FF 10
-					15 00 00 00 00 00 02 FB 01
-					15 00 00 00 00 00 02 51 FF
-					15 00 00 00 00 00 02 53 2C
-					15 01 00 00 00 00 02 55 02   /*mode switch*/
-					];
-				qcom,mdss-dsi-cabc-video-command = [
-					15 01 00 00 00 00 02 FF 23
-					15 00 00 00 00 00 02 FB 01
-					/*MOV_PWM DUTY*/
-					15 01 00 00 00 00 02 58 D9
-					15 00 00 00 00 00 02 59 CC
-					15 00 00 00 00 00 02 5A C0
-					15 00 00 00 00 00 02 5B B3
-					15 00 00 00 00 00 02 5C B2
-					15 00 00 00 00 00 02 5D B2
-					15 00 00 00 00 00 02 5E B2
-					15 00 00 00 00 00 02 5F A6
-					15 00 00 00 00 00 02 60 A5
-					15 00 00 00 00 00 02 61 A1
-					15 01 00 00 00 00 02 62 A0
-					15 00 00 00 00 00 02 63 98
-					15 00 00 00 00 00 02 64 90
-					15 00 00 00 00 00 02 65 8A
-					15 00 00 00 00 00 02 66 80
-					15 00 00 00 00 00 02 67 72
-					15 01 00 00 00 00 02 FF 10
-					15 00 00 00 00 00 02 FB 01
-					15 00 00 00 00 00 02 51 FF
-					15 00 00 00 00 00 02 53 2C
-					15 01 00 00 00 00 02 55 03   /*mode switch*/
-					];
-				qcom,mdss-dsi-cabc-off-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-cabc-ui-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-cabc-still-image-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-cabc-video-command-state = "dsi_lp_mode";
-				/*#endif ODM_LQ_EDIT*/
-				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
-			};
-		};
-	};
-};
-
-&dsi_nt36672c_boe_video {
-	qcom,esd-check-enabled;
-	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
-	qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 00];
-	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
-	qcom,mdss-dsi-panel-status-value = <0x9C>;
-	qcom,mdss-dsi-panel-on-check-value = <0x9C>;
-	qcom,mdss-dsi-panel-status-read-length = <1>;
-	qcom,mdss-dsi-panel-max-error-count = <3>;
-	qcom,mdss-dsi-t-clk-post = <0x00>;
-	qcom,mdss-dsi-t-clk-pre = <0x00>;
-	qcom,mdss-dsi-display-timings {
-		timing@0{
-			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09 09
-				09 06 02 04];
-			qcom,display-topology = <1 0 1>;
-			qcom,default-topology-index = <0>;
-		};
-	};
+                /* Topology & PHY (Merged) */
+                qcom,display-topology = <1 0 1>;
+                qcom,default-topology-index = <0>;
+                qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09 09 09 06 02 04];
+
+                qcom,mdss-dsi-pre-on-command=[
+                        29 01 00 00 00 00 02 FF C0   /*modified for VDD_TP power*/
+                        29 01 00 00 0A 00 02 48 1F
+                        29 01 00 00 00 00 02 FF C0
+                        29 01 00 00 00 00 02 4B 0E];
+
+                /* OPTIMIZATION: Switched to HS mode */
+                qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-on-command = [
+                        29 01 00 00 00 00 02 FF 10
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 B0 10
+                        29 01 00 00 00 00 02 C0 00       /*VESA off for C-PHY*/
+                        29 01 00 00 00 00 03 C2 1B A0
+
+                        29 01 00 00 00 00 02 FF 25
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 18 20     /*60hz :21 ; 90hz:20*/
+
+                        15 01 00 00 00 00 02 FF 2A  /*for switch 60hz TP*/
+                        15 01 00 00 00 00 02 FB 01
+                        15 01 00 00 00 00 02 27 80
+                        15 01 00 00 00 00 02 28 FD
+
+                        /* TP self-test */
+                        29 01 00 00 00 00 02 FF F0
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 5A 00
+                        29 01 00 00 00 00 02 A0 08
+                        29 01 00 00 00 00 02 FF D0
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 09 AD
+
+                        /* CABC SECTION */
+                        15 01 00 00 00 00 02 FF 10
+                        15 01 00 00 00 00 02 FB 01
+                        15 01 00 00 00 00 02 51 FF   /*keep pwm high when cabc off*/
+                        15 01 00 00 00 00 02 53 24
+                        15 01 00 00 00 00 02 FF 23
+                        15 01 00 00 00 00 02 FB 01
+
+                        15 01 00 00 00 00 02 0A 00
+                        15 01 00 00 00 00 02 0B 00
+                        15 01 00 00 00 00 02 0C 00
+                        15 01 00 00 00 00 02 0D 00
+
+                        15 01 00 00 00 00 02 11 01
+                        15 01 00 00 00 00 02 12 95
+                        15 01 00 00 00 00 02 15 68
+                        15 01 00 00 00 00 02 16 0B
+                        15 01 00 00 00 00 02 6F 00
+                        15 01 00 00 00 00 02 70 00
+                        15 01 00 00 00 00 02 71 00
+                        15 01 00 00 00 00 02 A0 11
+                        15 01 00 00 00 00 02 FF  F0
+                        15 01 00 00 00 00 02 FB 01
+                        15 01 00 00 00 00 02 D2 52
+                        /* END CABC */
+
+                        29 01 00 00 00 00 02 FF 24
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 E3 02
+                        29 01 00 00 00 00 02 FF D0
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 53 22
+                        29 01 00 00 00 00 02 54 02
+
+                        29 01 00 00 00 00 02 FF 23
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 07 20
+                        29 01 00 00 00 00 02 08 07
+                        29 01 00 00 00 00 02 09 04
+
+                        29 01 00 00 00 00 02 FF 10
+                        29 01 00 00 00 00 02 35 00
+                        05 01 00 00 46 00 02 11 00
+                        05 01 00 00 1E 00 02 29 00
+                    ];
+
+                qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-off-command =[
+                    29 01 00 00 00 00 02 FF 10
+                    29 01 00 00 00 00 02 FB 01
+                    05 01 00 00 14 00 02 28 00
+                    05 01 00 00 78 00 02 10 00
+                    ];
+
+                /* OPTIMIZATION: CABC commands switched to HS mode */
+                qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-off-command = [
+                    15 01 00 00 00 00 02 FF 10
+                    15 01 00 00 00 00 02 55 00
+                    ];
+
+                qcom,mdss-dsi-cabc-ui-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-ui-command = [
+                    15 01 00 00 00 00 02 FF 23
+                    15 00 00 00 00 00 02 FB 01
+                    /*UI_PWM DUTY*/
+                    15 01 00 00 00 00 02 30 FF
+                    15 00 00 00 00 00 02 31 FC
+                    15 00 00 00 00 00 02 32 F8
+                    15 00 00 00 00 00 02 33 F4
+                    15 00 00 00 00 00 02 34 F3
+                    15 00 00 00 00 00 02 35 F3
+                    15 00 00 00 00 00 02 36 F3
+                    15 00 00 00 00 00 02 37 F2
+                    15 00 00 00 00 00 02 38 F1
+                    15 00 00 00 00 00 02 39 F0
+                    15 01 00 00 00 00 02 3A EE
+                    15 00 00 00 00 00 02 3B EC
+                    15 00 00 00 00 00 02 3D EA
+                    15 00 00 00 00 00 02 3F E8
+                    15 00 00 00 00 00 02 40 E6
+                    15 00 00 00 10 00 02 41 E4
+                    15 01 00 00 00 00 02 FF 10
+                    15 00 00 00 00 00 02 FB 01
+                    15 00 00 00 00 00 02 51 FF
+                    15 00 00 00 00 00 02 53 2C
+                    15 01 00 00 00 00 02 55 01   /*mode switch*/
+                    ];
+
+                qcom,mdss-dsi-cabc-still-image-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-still-image-command = [
+                    15 01 00 00 00 00 02 FF 23
+                    15 00 00 00 00 00 02 FB 01
+                    /*Still_PWM DUTY*/
+                    15 01 00 00 00 00 02 45 E7
+                    15 00 00 00 00 00 02 46 E0
+                    15 00 00 00 00 00 02 47 D8
+                    15 00 00 00 00 00 02 48 CE
+                    15 00 00 00 00 00 02 49 CD
+                    15 00 00 00 00 00 02 4A CC
+                    15 00 00 00 00 00 02 4B CA
+                    15 00 00 00 00 00 02 4C C4
+                    15 00 00 00 00 00 02 4D C0
+                    15 00 00 00 00 00 02 4E BF
+                    15 01 00 00 00 00 02 4F BF
+                    15 00 00 00 00 00 02 50 BF
+                    15 00 00 00 00 00 02 51 BF
+                    15 00 00 00 00 00 02 52 BF
+                    15 00 00 00 00 00 02 53 BF
+                    15 00 00 00 00 00 02 54 BE
+                    15 01 00 00 00 00 02 FF 10
+                    15 00 00 00 00 00 02 FB 01
+                    15 00 00 00 00 00 02 51 FF
+                    15 00 00 00 00 00 02 53 2C
+                    15 01 00 00 00 00 02 55 02   /*mode switch*/
+                    ];
+
+                qcom,mdss-dsi-cabc-video-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-video-command = [
+                    15 01 00 00 00 00 02 FF 23
+                    15 00 00 00 00 00 02 FB 01
+                    /*MOV_PWM DUTY*/
+                    15 01 00 00 00 00 02 58 D9
+                    15 00 00 00 00 00 02 59 CC
+                    15 00 00 00 00 00 02 5A C0
+                    15 00 00 00 00 00 02 5B B3
+                    15 00 00 00 00 00 02 5C B2
+                    15 00 00 00 00 00 02 5D B2
+                    15 00 00 00 00 00 02 5E B2
+                    15 00 00 00 00 00 02 5F A6
+                    15 00 00 00 00 00 02 60 A5
+                    15 00 00 00 00 00 02 61 A1
+                    15 01 00 00 00 00 02 62 A0
+                    15 00 00 00 00 00 02 63 98
+                    15 00 00 00 00 00 02 64 90
+                    15 00 00 00 00 00 02 65 8A
+                    15 00 00 00 00 00 02 66 80
+                    15 00 00 00 00 00 02 67 72
+                    15 01 00 00 00 00 02 FF 10
+                    15 00 00 00 00 00 02 FB 01
+                    15 00 00 00 00 00 02 51 FF
+                    15 00 00 00 00 00 02 53 2C
+                    15 01 00 00 00 00 02 55 03   /*mode switch*/
+                    ];
+            };
+        };
+    };
 };
diff --git a/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-jdi-fhd-plus-video.dtsi b/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-jdi-fhd-plus-video.dtsi
index 7112e7d7babb..6d1169bdc727 100644
--- a/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-jdi-fhd-plus-video.dtsi
+++ b/arch/arm64/boot/dts/19721/dsi-panel-nt36672c-jdi-fhd-plus-video.dtsi
@@ -11,280 +11,297 @@
  */
 
 &mdss_mdp {
-	dsi_nt36672c_jdi_video: qcom,mdss_dsi_nt36672c_jdi_video {
-		qcom,mdss-dsi-panel-name =
-			"nt36672c jdi fhd plus video mode dsi panel";
-		qcom,mdss-dsi-panel-type = "dsi_video_mode";
-		qcom,mdss-dsi-virtual-channel-id = <0>;
-		qcom,mdss-dsi-stream = <0>;
-		qcom,mdss-dsi-bpp = <24>;
-		qcom,mdss-dsi-underflow-color = <0xff>;
-		qcom,mdss-dsi-border-color = <0>;
-		qcom,mdss-dsi-traffic-mode = "burst_mode";
-		qcom,mdss-dsi-bllp-eof-power-mode;
-		qcom,mdss-dsi-bllp-power-mode;
-		qcom,mdss-dsi-lane-0-state;
-		qcom,mdss-dsi-lane-1-state;
-		qcom,mdss-dsi-lane-2-state;
-		qcom,mdss-dsi-dma-trigger = "trigger_sw";
-		qcom,mdss-dsi-mdp-trigger = "none";
-		qcom,mdss-dsi-reset-sequence = <1 10>, <0 3>, <1 0>;
-		qcom,mdss-pan-physical-width-dimension = <69>;
-		qcom,mdss-pan-physical-height-dimension = <152>;
-		qcom,mdss-dsi-dma-schedule-line = <5>;
+    dsi_nt36672c_jdi_video: qcom,mdss_dsi_nt36672c_jdi_video {
+        qcom,mdss-dsi-panel-name = "nt36672c jdi fhd plus video mode dsi panel";
+        qcom,mdss-dsi-panel-type = "dsi_video_mode";
+        qcom,mdss-dsi-virtual-channel-id = <0>;
+        qcom,mdss-dsi-stream = <0>;
+        qcom,mdss-dsi-bpp = <24>;
+        qcom,mdss-dsi-underflow-color = <0xff>;
+        qcom,mdss-dsi-border-color = <0>;
+        qcom,mdss-dsi-traffic-mode = "burst_mode";
+        qcom,mdss-dsi-bllp-eof-power-mode;
+        qcom,mdss-dsi-bllp-power-mode;
 
-		qcom,mdss-dsi-lp11-init;
-		qcom,dsi-supported-dfps-list = <60 90 45>;
-		qcom,mdss-dsi-pan-enable-dynamic-fps;
-		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+        /* Lane Configuration */
+        qcom,mdss-dsi-lane-0-state;
+        qcom,mdss-dsi-lane-1-state;
+        qcom,mdss-dsi-lane-2-state;
 
-		qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
-		qcom,platform-te-gpio = <&tlmm 10 0>;
-		qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+        /* Trigger Controls */
+        qcom,mdss-dsi-dma-trigger = "trigger_sw";
+        qcom,mdss-dsi-mdp-trigger = "none";
+        qcom,mdss-dsi-reset-sequence = <1 10>, <0 3>, <1 0>;
 
-		oplus,is_19696_lcd;
-		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
-		qcom,mdss-dsi-bl-min-level = <1>;
-		qcom,mdss-dsi-bl-max-level = <4095>;
-                qcom,mdss-dsi-bl-normal-max-level = <2047>;
-		qcom,mdss-brightness-max-level =<2047>;
-		qcom,mdss-dsi-bl-default-level = <1024>;
-		oppo,dsi-brightness-remapping = <1    1>,
-							<2    18>,
-							<20   44>,
-							<50   58>,
-							<121  84>,
-							<200  118>,
-							<277  152>,
-							<355  190>,
-							<452  242>,
-							<605  348>,
-							<803  528>,
-							<1024 786>,
-							<1224 1116>,
-							<1425 1570>,
-							<1625 2170>,
-							<1823 2962>,
-							<2047 4095>;
+        /* Physical Dimensions */
+        qcom,mdss-pan-physical-width-dimension = <69>;
+        qcom,mdss-pan-physical-height-dimension = <152>;
+        qcom,mdss-dsi-dma-schedule-line = <5>;
 
-		qcom,mdss-dsi-panel-hdr-enabled;
-		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
-		       16000 13250 34500 7500 3000>;
-		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
-		qcom,mdss-dsi-panel-blackness-level = <1023>;
-		qcom,panel-cphy-mode;
-		oppo,bl_interpolate_nosub;
-		oppo,mdss-dsi-vendor-name = "nt36672c";
-		oppo,mdss-dsi-manufacture = "jdi vdo mode";
+        /* C-PHY & Init */
+        qcom,panel-cphy-mode;
+        qcom,mdss-dsi-lp11-init;
 
-		qcom,mdss-dsi-display-timings {
-			timing@0{
-				qcom,mdss-dsi-panel-width = <1080>;
-				qcom,mdss-dsi-panel-height = <2400>;
-				qcom,mdss-dsi-h-front-porch = <202>;
-				qcom,mdss-dsi-h-back-porch = <56>;
-				qcom,mdss-dsi-h-pulse-width = <12>;
-				qcom,mdss-dsi-h-sync-skew = <0>;
-				qcom,mdss-dsi-v-back-porch = <10>;
-				qcom,mdss-dsi-v-front-porch = <1291>;
-				qcom,mdss-dsi-v-pulse-width = <10>;
-				qcom,mdss-dsi-panel-framerate = <60>;
-				qcom,mdss-dsi-pre-on-command=[
-						29 01 00 00 00 00 02 FF C0   /*modified for VDD_TP power*/
-						29 01 00 00 0A 00 02 48 1F
-						29 01 00 00 00 00 02 FF C0
-						29 01 00 00 00 00 02 4B 0E];
-				qcom,mdss-dsi-on-command = [
+        /* Refresh Rate Config (Removed unsupported 45Hz) */
+        qcom,dsi-supported-dfps-list = <60 90>;
+        qcom,mdss-dsi-pan-enable-dynamic-fps;
+        qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
 
-						29 01 00 00 00 00 02 FF 10
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 B0 10
-						29 01 00 00 00 00 02 C0 00       /*VESA off for C-PHY*/
-						29 01 00 00 00 00 03 C2 1B A0
+        /* Hardware Resources */
+        qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+        qcom,platform-te-gpio = <&tlmm 10 0>;
+        qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
 
-						29 01 00 00 00 00 02 FF 25
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 18 20     /*60hz :21 ; 90hz:20*/
+        /* Backlight & Brightness Control */
+        oplus,is_19696_lcd;
+        qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+        qcom,mdss-dsi-bl-min-level = <1>;
+        qcom,mdss-dsi-bl-max-level = <4095>;
+        qcom,mdss-dsi-bl-normal-max-level = <2047>;
+        qcom,mdss-brightness-max-level = <2047>;
+        qcom,mdss-dsi-bl-default-level = <1024>;
 
-						15 01 00 00 00 00 02 FF 2A  /*for switch 60hz TP*/
-						15 01 00 00 00 00 02 FB 01
-						15 01 00 00 00 00 02 27 80
-						15 01 00 00 00 00 02 28 0A
+        oppo,dsi-brightness-remapping = <1    1>,
+                            <2    18>,
+                            <20   44>,
+                            <50   58>,
+                            <121  84>,
+                            <200  118>,
+                            <277  152>,
+                            <355  190>,
+                            <452  242>,
+                            <605  348>,
+                            <803  528>,
+                            <1024 786>,
+                            <1224 1116>,
+                            <1425 1570>,
+                            <1625 2170>,
+                            <1823 2962>,
+                            <2047 4095>;
+
+        /* HDR & Color */
+        qcom,mdss-dsi-panel-hdr-enabled;
+        qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+               16000 13250 34500 7500 3000>;
+        qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+        qcom,mdss-dsi-panel-blackness-level = <1023>;
+
+        /* Vendor Info */
+        oppo,bl_interpolate_nosub;
+        oppo,mdss-dsi-vendor-name = "nt36672c";
+        oppo,mdss-dsi-manufacture = "jdi vdo mode";
+
+        /* ESD Recovery / Status Check (Merged from separate node) */
+        qcom,esd-check-enabled;
+        qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+        qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 00];
+        qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; /* Keep LP for status read stability */
+        qcom,mdss-dsi-panel-status-value = <0x9C>;
+        qcom,mdss-dsi-panel-on-check-value = <0x9C>;
+        qcom,mdss-dsi-panel-status-read-length = <1>;
+        qcom,mdss-dsi-panel-max-error-count = <3>;
+
+        /* Clock Adjustments */
+        qcom,mdss-dsi-t-clk-post = <0x00>;
+        qcom,mdss-dsi-t-clk-pre = <0x00>;
+
+        qcom,mdss-dsi-display-timings {
+            timing@0 {
+                qcom,mdss-dsi-panel-width = <1080>;
+                qcom,mdss-dsi-panel-height = <2400>;
+                qcom,mdss-dsi-h-front-porch = <202>;
+                qcom,mdss-dsi-h-back-porch = <56>;
+                qcom,mdss-dsi-h-pulse-width = <12>;
+                qcom,mdss-dsi-h-sync-skew = <0>;
+                qcom,mdss-dsi-v-back-porch = <10>;
+                qcom,mdss-dsi-v-front-porch = <1291>;
+                qcom,mdss-dsi-v-pulse-width = <10>;
+                qcom,mdss-dsi-panel-framerate = <60>;
+
+                /* Topology & PHY (Merged) */
+                qcom,display-topology = <1 0 1>;
+                qcom,default-topology-index = <0>;
+                qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09 09
+                    09 06 02 04];
+
+                qcom,mdss-dsi-pre-on-command=[
+                        29 01 00 00 00 00 02 FF C0   /*modified for VDD_TP power*/
+                        29 01 00 00 0A 00 02 48 1F
+                        29 01 00 00 00 00 02 FF C0
+                        29 01 00 00 00 00 02 4B 0E];
+
+                /* OPTIMIZATION: Switched ON commands to HS mode */
+                qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-on-command = [
+                        29 01 00 00 00 00 02 FF 10
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 B0 10
+                        29 01 00 00 00 00 02 C0 00       /*VESA off for C-PHY*/
+                        29 01 00 00 00 00 03 C2 1B A0
+
+                        29 01 00 00 00 00 02 FF 25
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 18 20     /*60hz :21 ; 90hz:20*/
+
+                        15 01 00 00 00 00 02 FF 2A  /*for switch 60hz TP*/
+                        15 01 00 00 00 00 02 FB 01
+                        15 01 00 00 00 00 02 27 80
+                        15 01 00 00 00 00 02 28 0A
 
 
-						29 01 00 00 00 00 02 FF F0		/*modified for TP self-test*/
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 5A 00
-						29 01 00 00 00 00 02 A0 08
-						29 01 00 00 00 00 02 FF D0
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 09 AD
+                        29 01 00 00 00 00 02 FF F0      /*modified for TP self-test*/
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 5A 00
+                        29 01 00 00 00 00 02 A0 08
+                        29 01 00 00 00 00 02 FF D0
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 09 AD
 
-						/*#ifdef ODM_LQ_EDIT*/
-						/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
-						15 01 00 00 00 00 02 FF 10
-						15 01 00 00 00 00 02 FB 01
-						15 01 00 00 00 00 02 51 FF   /*keep pwm high when cabc off*/
-						15 01 00 00 00 00 02 53 24
-						15 01 00 00 00 00 02 FF 23
-						15 01 00 00 00 00 02 FB 01
+                        /* CABC SECTION */
+                        15 01 00 00 00 00 02 FF 10
+                        15 01 00 00 00 00 02 FB 01
+                        15 01 00 00 00 00 02 51 FF   /*keep pwm high when cabc off*/
+                        15 01 00 00 00 00 02 53 24
+                        15 01 00 00 00 00 02 FF 23
+                        15 01 00 00 00 00 02 FB 01
 
-						15 01 00 00 00 00 02 0A 00
-						15 01 00 00 00 00 02 0B 00
-						15 01 00 00 00 00 02 0C 00
-						15 01 00 00 00 00 02 0D 00
+                        15 01 00 00 00 00 02 0A 00
+                        15 01 00 00 00 00 02 0B 00
+                        15 01 00 00 00 00 02 0C 00
+                        15 01 00 00 00 00 02 0D 00
 
-						15 01 00 00 00 00 02 11 01
-						15 01 00 00 00 00 02 12 95
-						15 01 00 00 00 00 02 15 68
-						15 01 00 00 00 00 02 16 0B
-						15 01 00 00 00 00 02 6F 00
-						15 01 00 00 00 00 02 70 00
-						15 01 00 00 00 00 02 71 00
-						15 01 00 00 00 00 02 A0 11
-						15 01 00 00 00 00 02 FF  F0
-						15 01 00 00 00 00 02 FB 01
-						15 01 00 00 00 00 02 D2 52
-						/*#endif ODM_LQ_EDIT*/
+                        15 01 00 00 00 00 02 11 01
+                        15 01 00 00 00 00 02 12 95
+                        15 01 00 00 00 00 02 15 68
+                        15 01 00 00 00 00 02 16 0B
+                        15 01 00 00 00 00 02 6F 00
+                        15 01 00 00 00 00 02 70 00
+                        15 01 00 00 00 00 02 71 00
+                        15 01 00 00 00 00 02 A0 11
+                        15 01 00 00 00 00 02 FF  F0
+                        15 01 00 00 00 00 02 FB 01
+                        15 01 00 00 00 00 02 D2 52
+                        /* END CABC SECTION */
 
-						29 01 00 00 00 00 02 FF 24
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 E3 02
-						29 01 00 00 00 00 02 FF D0
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 53 22
-						29 01 00 00 00 00 02 54 02
+                        29 01 00 00 00 00 02 FF 24
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 E3 02
+                        29 01 00 00 00 00 02 FF D0
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 53 22
+                        29 01 00 00 00 00 02 54 02
 
-						29 01 00 00 00 00 02 FF 23
-						29 01 00 00 00 00 02 FB 01
-						29 01 00 00 00 00 02 07 20
-						29 01 00 00 00 00 02 08 07
-						29 01 00 00 00 00 02 09 04
+                        29 01 00 00 00 00 02 FF 23
+                        29 01 00 00 00 00 02 FB 01
+                        29 01 00 00 00 00 02 07 20
+                        29 01 00 00 00 00 02 08 07
+                        29 01 00 00 00 00 02 09 04
 
-						29 01 00 00 00 00 02 FF 10
-						29 01 00 00 00 00 02 35 00
-						05 01 00 00 46 00 02 11 00
-						05 01 00 00 1E 00 02 29 00
-					];
-				qcom,mdss-dsi-off-command =[
-					29 01 00 00 00 00 02 FF 10
-					29 01 00 00 00 00 02 FB 01
-					05 01 00 00 14 00 02 28 00
-					05 01 00 00 78 00 02 10 00
-					];
-				/*#ifdef ODM_LQ_EDIT*/
-				/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
-				qcom,mdss-dsi-cabc-off-command = [
-					15 01 00 00 00 00 02 FF 10
-					15 01 00 00 00 00 02 55 00
-					];
-				qcom,mdss-dsi-cabc-ui-command = [
-					15 01 00 00 00 00 02 FF 23
-					15 00 00 00 00 00 02 FB 01
-					/*UI_PWM DUTY*/
-					15 01 00 00 00 00 02 30 FF
-					15 00 00 00 00 00 02 31 FC
-					15 00 00 00 00 00 02 32 F8
-					15 00 00 00 00 00 02 33 F4
-					15 00 00 00 00 00 02 34 F3
-					15 00 00 00 00 00 02 35 F3
-					15 00 00 00 00 00 02 36 F3
-					15 00 00 00 00 00 02 37 F2
-					15 00 00 00 00 00 02 38 F1
-					15 00 00 00 00 00 02 39 F0
-					15 01 00 00 00 00 02 3A EE
-					15 00 00 00 00 00 02 3B EC
-					15 00 00 00 00 00 02 3D EA
-					15 00 00 00 00 00 02 3F E8
-					15 00 00 00 00 00 02 40 E6
-					15 00 00 00 10 00 02 41 E4
-					15 01 00 00 00 00 02 FF 10
-					15 00 00 00 00 00 02 FB 01
-					15 00 00 00 00 00 02 51 FF
-					15 00 00 00 00 00 02 53 2C
-					15 01 00 00 00 00 02 55 01   /*mode switch*/
-					];
-				qcom,mdss-dsi-cabc-still-image-command = [
-					15 01 00 00 00 00 02 FF 23
-					15 00 00 00 00 00 02 FB 01
-					/*Still_PWM DUTY*/
-					15 01 00 00 00 00 02 45 E7
-					15 00 00 00 00 00 02 46 E0
-					15 00 00 00 00 00 02 47 D8
-					15 00 00 00 00 00 02 48 CE
-					15 00 00 00 00 00 02 49 CD
-					15 00 00 00 00 00 02 4A CC
-					15 00 00 00 00 00 02 4B CA
-					15 00 00 00 00 00 02 4C C4
-					15 00 00 00 00 00 02 4D C0
-					15 00 00 00 00 00 02 4E BF
-					15 01 00 00 00 00 02 4F BF
-					15 00 00 00 00 00 02 50 BF
-					15 00 00 00 00 00 02 51 BF
-					15 00 00 00 00 00 02 52 BF
-					15 00 00 00 00 00 02 53 BF
-					15 00 00 00 00 00 02 54 BE
-					15 01 00 00 00 00 02 FF 10
-					15 00 00 00 00 00 02 FB 01
-					15 00 00 00 00 00 02 51 FF
-					15 00 00 00 00 00 02 53 2C
-					15 01 00 00 00 00 02 55 02   /*mode switch*/
-					];
-				qcom,mdss-dsi-cabc-video-command = [
-					15 01 00 00 00 00 02 FF 23
-					15 00 00 00 00 00 02 FB 01
-					/*MOV_PWM DUTY*/
-					15 01 00 00 00 00 02 58 D9
-					15 00 00 00 00 00 02 59 CC
-					15 00 00 00 00 00 02 5A C0
-					15 00 00 00 00 00 02 5B B3
-					15 00 00 00 00 00 02 5C B2
-					15 00 00 00 00 00 02 5D B2
-					15 00 00 00 00 00 02 5E B2
-					15 00 00 00 00 00 02 5F A6
-					15 00 00 00 00 00 02 60 A5
-					15 00 00 00 00 00 02 61 A1
-					15 01 00 00 00 00 02 62 A0
-					15 00 00 00 00 00 02 63 98
-					15 00 00 00 00 00 02 64 90
-					15 00 00 00 00 00 02 65 8A
-					15 00 00 00 00 00 02 66 80
-					15 00 00 00 00 00 02 67 72
-					15 01 00 00 00 00 02 FF 10
-					15 00 00 00 00 00 02 FB 01
-					15 00 00 00 00 00 02 51 FF
-					15 00 00 00 00 00 02 53 2C
-					15 01 00 00 00 00 02 55 03   /*mode switch*/
-					];
-				qcom,mdss-dsi-cabc-off-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-cabc-ui-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-cabc-still-image-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-cabc-video-command-state = "dsi_lp_mode";
-				/*#endif ODM_LQ_EDIT*/
-				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
-			};
-		};
-	};
-};
-
-&dsi_nt36672c_jdi_video {
-	qcom,esd-check-enabled;
-	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
-	qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 00];
-	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
-	qcom,mdss-dsi-panel-status-value = <0x9C>;
-	qcom,mdss-dsi-panel-on-check-value = <0x9C>;
-	qcom,mdss-dsi-panel-status-read-length = <1>;
-	qcom,mdss-dsi-panel-max-error-count = <3>;
-	qcom,mdss-dsi-t-clk-post = <0x00>;
-	qcom,mdss-dsi-t-clk-pre = <0x00>;
-	qcom,mdss-dsi-display-timings {
-		timing@0{
-			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09 09
-				09 06 02 04];
-			qcom,display-topology = <1 0 1>;
-			qcom,default-topology-index = <0>;
-		};
-	};
+                        29 01 00 00 00 00 02 FF 10
+                        29 01 00 00 00 00 02 35 00
+                        05 01 00 00 46 00 02 11 00
+                        05 01 00 00 1E 00 02 29 00
+                    ];
+
+                qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-off-command =[
+                    29 01 00 00 00 00 02 FF 10
+                    29 01 00 00 00 00 02 FB 01
+                    05 01 00 00 14 00 02 28 00
+                    05 01 00 00 78 00 02 10 00
+                    ];
+
+                /* OPTIMIZATION: CABC commands switched to HS mode */
+                qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-off-command = [
+                    15 01 00 00 00 00 02 FF 10
+                    15 01 00 00 00 00 02 55 00
+                    ];
+
+                qcom,mdss-dsi-cabc-ui-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-ui-command = [
+                    15 01 00 00 00 00 02 FF 23
+                    15 00 00 00 00 00 02 FB 01
+                    /*UI_PWM DUTY*/
+                    15 01 00 00 00 00 02 30 FF
+                    15 00 00 00 00 00 02 31 FC
+                    15 00 00 00 00 00 02 32 F8
+                    15 00 00 00 00 00 02 33 F4
+                    15 00 00 00 00 00 02 34 F3
+                    15 00 00 00 00 00 02 35 F3
+                    15 00 00 00 00 00 02 36 F3
+                    15 00 00 00 00 00 02 37 F2
+                    15 00 00 00 00 00 02 38 F1
+                    15 00 00 00 00 00 02 39 F0
+                    15 01 00 00 00 00 02 3A EE
+                    15 00 00 00 00 00 02 3B EC
+                    15 00 00 00 00 00 02 3D EA
+                    15 00 00 00 00 00 02 3F E8
+                    15 00 00 00 00 00 02 40 E6
+                    15 00 00 00 10 00 02 41 E4
+                    15 01 00 00 00 00 02 FF 10
+                    15 00 00 00 00 00 02 FB 01
+                    15 00 00 00 00 00 02 51 FF
+                    15 00 00 00 00 00 02 53 2C
+                    15 01 00 00 00 00 02 55 01   /*mode switch*/
+                    ];
+
+                qcom,mdss-dsi-cabc-still-image-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-still-image-command = [
+                    15 01 00 00 00 00 02 FF 23
+                    15 00 00 00 00 00 02 FB 01
+                    /*Still_PWM DUTY*/
+                    15 01 00 00 00 00 02 45 E7
+                    15 00 00 00 00 00 02 46 E0
+                    15 00 00 00 00 00 02 47 D8
+                    15 00 00 00 00 00 02 48 CE
+                    15 00 00 00 00 00 02 49 CD
+                    15 00 00 00 00 00 02 4A CC
+                    15 00 00 00 00 00 02 4B CA
+                    15 00 00 00 00 00 02 4C C4
+                    15 00 00 00 00 00 02 4D C0
+                    15 00 00 00 00 00 02 4E BF
+                    15 01 00 00 00 00 02 4F BF
+                    15 00 00 00 00 00 02 50 BF
+                    15 00 00 00 00 00 02 51 BF
+                    15 00 00 00 00 00 02 52 BF
+                    15 00 00 00 00 00 02 53 BF
+                    15 00 00 00 00 00 02 54 BE
+                    15 01 00 00 00 00 02 FF 10
+                    15 00 00 00 00 00 02 FB 01
+                    15 00 00 00 00 00 02 51 FF
+                    15 00 00 00 00 00 02 53 2C
+                    15 01 00 00 00 00 02 55 02   /*mode switch*/
+                    ];
+
+                qcom,mdss-dsi-cabc-video-command-state = "dsi_hs_mode";
+                qcom,mdss-dsi-cabc-video-command = [
+                    15 01 00 00 00 00 02 FF 23
+                    15 00 00 00 00 00 02 FB 01
+                    /*MOV_PWM DUTY*/
+                    15 01 00 00 00 00 02 58 D9
+                    15 00 00 00 00 00 02 59 CC
+                    15 00 00 00 00 00 02 5A C0
+                    15 00 00 00 00 00 02 5B B3
+                    15 00 00 00 00 00 02 5C B2
+                    15 00 00 00 00 00 02 5D B2
+                    15 00 00 00 00 00 02 5E B2
+                    15 00 00 00 00 00 02 5F A6
+                    15 00 00 00 00 00 02 60 A5
+                    15 00 00 00 00 00 02 61 A1
+                    15 01 00 00 00 00 02 62 A0
+                    15 00 00 00 00 00 02 63 98
+                    15 00 00 00 00 00 02 64 90
+                    15 00 00 00 00 00 02 65 8A
+                    15 00 00 00 00 00 02 66 80
+                    15 00 00 00 00 00 02 67 72
+                    15 01 00 00 00 00 02 FF 10
+                    15 00 00 00 00 00 02 FB 01
+                    15 00 00 00 00 00 02 51 FF
+                    15 00 00 00 00 00 02 53 2C
+                    15 01 00 00 00 00 02 55 03   /*mode switch*/
+                    ];
+            };
+        };
+    };
 };
diff --git a/arch/arm64/boot/dts/19721/sdmmagpie-gpu.dtsi b/arch/arm64/boot/dts/19721/sdmmagpie-gpu.dtsi
index f07018b9d798..8293bdf2fb1c 100644
--- a/arch/arm64/boot/dts/19721/sdmmagpie-gpu.dtsi
+++ b/arch/arm64/boot/dts/19721/sdmmagpie-gpu.dtsi
@@ -68,7 +68,6 @@
 
 		/* <HZ/12> */
 		qcom,idle-timeout = <80>;
-		qcom,no-nap;
 
 		qcom,highest-bank-bit = <14>;
 
diff --git a/arch/arm64/boot/dts/19771/atoll.dtsi b/arch/arm64/boot/dts/19771/atoll.dtsi
index 771bf059bae7..f1c1d9e142b6 100644
--- a/arch/arm64/boot/dts/19771/atoll.dtsi
+++ b/arch/arm64/boot/dts/19771/atoll.dtsi
@@ -674,7 +674,7 @@
 	};
 
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mitigations=off kpti=0 audit=0 nowhere cgroup_disable=memory dk=balanced";
 	};
 
 	soc: soc { };
@@ -818,6 +818,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU0>;
+		status = "disabled";
 	};
 
 	jtag_mm1: jtagmm@7140000 {
@@ -829,6 +830,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU1>;
+		status = "disabled";
 	};
 
 	jtag_mm2: jtagmm@7240000 {
@@ -840,6 +842,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU2>;
+		status = "disabled";
 	};
 
 	jtag_mm3: jtagmm@7340000 {
@@ -851,6 +854,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU3>;
+		status = "disabled";
 	};
 
 	jtag_mm4: jtagmm@7440000 {
@@ -862,6 +866,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU4>;
+		status = "disabled";
 	};
 
 	jtag_mm5: jtagmm@7540000 {
@@ -873,6 +878,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU5>;
+		status = "disabled";
 	};
 
 	jtag_mm6: jtagmm@7640000 {
@@ -884,6 +890,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU6>;
+		status = "disabled";
 	};
 
 	jtag_mm7: jtagmm@7740000 {
@@ -895,6 +902,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU7>;
+		status = "disabled";
 	};
 
 	qcom,msm-imem@146aa000 {
@@ -1536,7 +1544,7 @@
 	};
     //#endif /* FEATURE_OPPO_NV_BACKUP */
 	//#endif /* VENDOR_EDIT */
-	
+
 	pil_modem: qcom,mss@4080000 {
 		compatible = "qcom,pil-tz-generic";
 		reg = <0x4080000 0x100>;
@@ -2008,6 +2016,7 @@
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
+		status = "disabled";
 
 		rpmh {
 			qcom,dump-size = <0x2000000>;
@@ -2332,7 +2341,7 @@
 
 				msm_cdsp_rm: qcom,msm_cdsp_rm {
 					compatible = "qcom,msm-cdsp-rm";
-					qcom,qos-latency-us = <44>;
+					qcom,qos-latency-us = <30>;
 					qcom,qos-maxhold-ms = <20>;
 					qcom,compute-cx-limit-en;
 					qcom,compute-priority-mode = <2>;
@@ -3243,10 +3252,10 @@
 		qcom,target-dev = <&cpu0_cpu_l3_lat>;
 		qcom,cachemiss-ev = <0x17>;
 		qcom,core-dev-table =
-			<  768000  300000000 >,
-			< 1017600  556800000 >,
-			< 1248000  806400000 >,
-			< 1516800  940800000 >,
+			<  768000  556800000 >,
+			< 1017600  806400000 >,
+			< 1248000  940800000 >,
+			< 1516800 1209600000 >,
 			< 1804800 1401000000 >;
 	};
 
@@ -3263,11 +3272,11 @@
 		qcom,target-dev = <&cpu6_cpu_l3_lat>;
 		qcom,cachemiss-ev = <0x17>;
 		qcom,core-dev-table =
-			< 1113600  556800000 >,
-			< 1267200  806400000 >,
-			< 1555200  940800000 >,
-			< 1708800 1209600000 >,
-			< 1900800 1401000000 >,
+			< 1113600  806400000 >,
+			< 1267200  940800000 >,
+			< 1555200 1209600000 >,
+			< 1708800 1401000000 >,
+			< 1900800 1459000000 >,
 			< 2400000 1459000000 >;
 	};
 
@@ -3335,11 +3344,11 @@
 		qcom,target-dev = <&cpu0_llcc_ddr_lat>;
 		qcom,cachemiss-ev = <0x1000>;
 		qcom,core-dev-table =
-			<  768000 MHZ_TO_MBPS( 300, 4) >,
-			< 1017600 MHZ_TO_MBPS( 451, 4) >,
-			< 1248000 MHZ_TO_MBPS( 547, 4) >,
-			< 1516800 MHZ_TO_MBPS( 768, 4) >,
-			< 1804800 MHZ_TO_MBPS(1017, 4) >;
+			<  768000 MHZ_TO_MBPS( 547, 4) >,
+			< 1017600 MHZ_TO_MBPS( 768, 4) >,
+			< 1248000 MHZ_TO_MBPS(1017, 4) >,
+			< 1516800 MHZ_TO_MBPS(1353, 4) >,
+			< 1804800 MHZ_TO_MBPS(1555, 4) >;
 	};
 
 	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
@@ -3357,8 +3366,8 @@
 		qcom,target-dev = <&cpu6_llcc_ddr_lat>;
 		qcom,cachemiss-ev = <0x1000>;
 		qcom,core-dev-table =
-			< 1113600 MHZ_TO_MBPS( 547, 4) >,
-			< 1267200 MHZ_TO_MBPS(1017, 4) >,
+			< 1113600 MHZ_TO_MBPS(1017, 4) >,
+			< 1267200 MHZ_TO_MBPS(1353, 4) >,
 			< 1708800 MHZ_TO_MBPS(1555, 4) >,
 			< 2208000 MHZ_TO_MBPS(1804, 4) >,
 			< 2400000 MHZ_TO_MBPS(2133, 4) >;
@@ -3378,10 +3387,10 @@
 		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
 		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
 		qcom,core-dev-table =
-			<  768000 MHZ_TO_MBPS( 300, 4) >,
-			< 1248000 MHZ_TO_MBPS( 451, 4) >,
-			< 1516800 MHZ_TO_MBPS( 547, 4) >,
-			< 1804800 MHZ_TO_MBPS( 768, 4) >;
+			<  768000 MHZ_TO_MBPS( 547, 4) >,
+			< 1248000 MHZ_TO_MBPS(1017, 4) >,
+			< 1516800 MHZ_TO_MBPS(1353, 4) >,
+			< 1804800 MHZ_TO_MBPS(1555, 4) >;
 	};
 
 	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
@@ -3398,9 +3407,9 @@
 		qcom,cpulist = <&CPU6 &CPU7>;
 		qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
 		qcom,core-dev-table =
-			< 1267200 MHZ_TO_MBPS( 547, 4) >,
-			< 1555200 MHZ_TO_MBPS( 768, 4) >,
-			< 1708800 MHZ_TO_MBPS(1017, 4) >,
+			< 1267200 MHZ_TO_MBPS( 768, 4) >,
+			< 1555200 MHZ_TO_MBPS(1017, 4) >,
+			< 1708800 MHZ_TO_MBPS(1353, 4) >,
 			< 1900800 MHZ_TO_MBPS(1555, 4) >,
 			< 2208000 MHZ_TO_MBPS(1804, 4) >,
 			< 2400000 MHZ_TO_MBPS(2133, 4) >;
@@ -3945,8 +3954,8 @@
 
 			qcom,speed-bin = <159>;
 
-			qcom,initial-pwrlevel = <5>;
-			qcom,ca-target-pwrlevel = <4>;
+			qcom,initial-pwrlevel = <6>;
+			qcom,ca-target-pwrlevel = <5>;
 
 			/* NOM_L1 */
 			qcom,gpu-pwrlevel@0 {
@@ -4002,9 +4011,18 @@
 				qcom,bus-max = <7>;
 			};
 
-			/* XO */
+			/* MIN SVS */
 			qcom,gpu-pwrlevel@6 {
 				reg = <6>;
+				qcom,gpu-freq = <180000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <5>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <0>;
 				qcom,bus-freq = <0>;
 				qcom,bus-min = <0>;
diff --git a/arch/arm64/boot/dts/19771/sdmmagpie-gpu.dtsi b/arch/arm64/boot/dts/19771/sdmmagpie-gpu.dtsi
index f07018b9d798..8293bdf2fb1c 100644
--- a/arch/arm64/boot/dts/19771/sdmmagpie-gpu.dtsi
+++ b/arch/arm64/boot/dts/19771/sdmmagpie-gpu.dtsi
@@ -68,7 +68,6 @@
 
 		/* <HZ/12> */
 		qcom,idle-timeout = <80>;
-		qcom,no-nap;
 
 		qcom,highest-bank-bit = <14>;
 
diff --git a/arch/arm64/boot/dts/206B1/atoll.dtsi b/arch/arm64/boot/dts/206B1/atoll.dtsi
index ec84fce70792..1d1bc0e0ed19 100644
--- a/arch/arm64/boot/dts/206B1/atoll.dtsi
+++ b/arch/arm64/boot/dts/206B1/atoll.dtsi
@@ -3962,8 +3962,8 @@
 
 			qcom,speed-bin = <159>;
 
-			qcom,initial-pwrlevel = <5>;
-			qcom,ca-target-pwrlevel = <4>;
+			qcom,initial-pwrlevel = <6>;
+			qcom,ca-target-pwrlevel = <5>;
 
 			/* NOM_L1 */
 			qcom,gpu-pwrlevel@0 {
@@ -4019,9 +4019,18 @@
 				qcom,bus-max = <7>;
 			};
 
-			/* XO */
+			/* MIN SVS */
 			qcom,gpu-pwrlevel@6 {
 				reg = <6>;
+				qcom,gpu-freq = <180000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <5>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <0>;
 				qcom,bus-freq = <0>;
 				qcom,bus-min = <0>;
diff --git a/arch/arm64/boot/dts/206B1/sdmmagpie-gpu.dtsi b/arch/arm64/boot/dts/206B1/sdmmagpie-gpu.dtsi
index f07018b9d798..8293bdf2fb1c 100644
--- a/arch/arm64/boot/dts/206B1/sdmmagpie-gpu.dtsi
+++ b/arch/arm64/boot/dts/206B1/sdmmagpie-gpu.dtsi
@@ -68,7 +68,6 @@
 
 		/* <HZ/12> */
 		qcom,idle-timeout = <80>;
-		qcom,no-nap;
 
 		qcom,highest-bank-bit = <14>;
 
diff --git a/arch/arm64/boot/dts/20711/atoll.dtsi b/arch/arm64/boot/dts/20711/atoll.dtsi
index cccb0acae280..53183c3bee99 100644
--- a/arch/arm64/boot/dts/20711/atoll.dtsi
+++ b/arch/arm64/boot/dts/20711/atoll.dtsi
@@ -697,7 +697,7 @@
 	};
 
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mitigations=off kpti=0 audit=0 nowhere cgroup_disable=memory dk=balanced";
 	};
 
 	soc: soc { };
@@ -841,6 +841,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU0>;
+		status = "disabled";
 	};
 
 	jtag_mm1: jtagmm@7140000 {
@@ -852,6 +853,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU1>;
+		status = "disabled";
 	};
 
 	jtag_mm2: jtagmm@7240000 {
@@ -863,6 +865,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU2>;
+		status = "disabled";
 	};
 
 	jtag_mm3: jtagmm@7340000 {
@@ -874,6 +877,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU3>;
+		status = "disabled";
 	};
 
 	jtag_mm4: jtagmm@7440000 {
@@ -885,6 +889,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU4>;
+		status = "disabled";
 	};
 
 	jtag_mm5: jtagmm@7540000 {
@@ -896,6 +901,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU5>;
+		status = "disabled";
 	};
 
 	jtag_mm6: jtagmm@7640000 {
@@ -907,6 +913,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU6>;
+		status = "disabled";
 	};
 
 	jtag_mm7: jtagmm@7740000 {
@@ -918,6 +925,7 @@
 		clock-names = "core_clk";
 
 		qcom,coresight-jtagmm-cpu = <&CPU7>;
+		status = "disabled";
 	};
 
 	qcom,msm-imem@146aa000 {
@@ -1559,7 +1567,7 @@
 	};
     //#endif /* FEATURE_OPPO_NV_BACKUP */
 	//#endif /* VENDOR_EDIT */
-	
+
 	pil_modem: qcom,mss@4080000 {
 		compatible = "qcom,pil-tz-generic";
 		reg = <0x4080000 0x100>;
@@ -2031,6 +2039,7 @@
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
+		status = "disabled";
 
 		rpmh {
 			qcom,dump-size = <0x2000000>;
@@ -2355,7 +2364,7 @@
 
 				msm_cdsp_rm: qcom,msm_cdsp_rm {
 					compatible = "qcom,msm-cdsp-rm";
-					qcom,qos-latency-us = <44>;
+					qcom,qos-latency-us = <30>;
 					qcom,qos-maxhold-ms = <20>;
 					qcom,compute-cx-limit-en;
 					qcom,compute-priority-mode = <2>;
@@ -3265,10 +3274,10 @@
 		qcom,target-dev = <&cpu0_cpu_l3_lat>;
 		qcom,cachemiss-ev = <0x17>;
 		qcom,core-dev-table =
-			<  768000  300000000 >,
-			< 1017600  556800000 >,
-			< 1248000  806400000 >,
-			< 1516800  940800000 >,
+			<  768000  556800000 >,
+			< 1017600  806400000 >,
+			< 1248000  940800000 >,
+			< 1516800 1209600000 >,
 			< 1804800 1401000000 >;
 	};
 
@@ -3285,11 +3294,11 @@
 		qcom,target-dev = <&cpu6_cpu_l3_lat>;
 		qcom,cachemiss-ev = <0x17>;
 		qcom,core-dev-table =
-			< 1113600  556800000 >,
-			< 1267200  806400000 >,
-			< 1555200  940800000 >,
-			< 1708800 1209600000 >,
-			< 1900800 1401000000 >,
+			< 1113600  806400000 >,
+			< 1267200  940800000 >,
+			< 1555200 1209600000 >,
+			< 1708800 1401000000 >,
+			< 1900800 1459000000 >,
 			< 2400000 1459000000 >;
 	};
 
@@ -3357,11 +3366,11 @@
 		qcom,target-dev = <&cpu0_llcc_ddr_lat>;
 		qcom,cachemiss-ev = <0x1000>;
 		qcom,core-dev-table =
-			<  768000 MHZ_TO_MBPS( 300, 4) >,
-			< 1017600 MHZ_TO_MBPS( 451, 4) >,
-			< 1248000 MHZ_TO_MBPS( 547, 4) >,
-			< 1516800 MHZ_TO_MBPS( 768, 4) >,
-			< 1804800 MHZ_TO_MBPS(1017, 4) >;
+			<  768000 MHZ_TO_MBPS( 547, 4) >,
+			< 1017600 MHZ_TO_MBPS( 768, 4) >,
+			< 1248000 MHZ_TO_MBPS(1017, 4) >,
+			< 1516800 MHZ_TO_MBPS(1353, 4) >,
+			< 1804800 MHZ_TO_MBPS(1555, 4) >;
 	};
 
 	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
@@ -3379,8 +3388,8 @@
 		qcom,target-dev = <&cpu6_llcc_ddr_lat>;
 		qcom,cachemiss-ev = <0x1000>;
 		qcom,core-dev-table =
-			< 1113600 MHZ_TO_MBPS( 547, 4) >,
-			< 1267200 MHZ_TO_MBPS(1017, 4) >,
+			< 1113600 MHZ_TO_MBPS(1017, 4) >,
+			< 1267200 MHZ_TO_MBPS(1353, 4) >,
 			< 1708800 MHZ_TO_MBPS(1555, 4) >,
 			< 2208000 MHZ_TO_MBPS(1804, 4) >,
 			< 2400000 MHZ_TO_MBPS(2133, 4) >;
@@ -3400,10 +3409,10 @@
 		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
 		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
 		qcom,core-dev-table =
-			<  768000 MHZ_TO_MBPS( 300, 4) >,
-			< 1248000 MHZ_TO_MBPS( 451, 4) >,
-			< 1516800 MHZ_TO_MBPS( 547, 4) >,
-			< 1804800 MHZ_TO_MBPS( 768, 4) >;
+			<  768000 MHZ_TO_MBPS( 547, 4) >,
+			< 1248000 MHZ_TO_MBPS(1017, 4) >,
+			< 1516800 MHZ_TO_MBPS(1353, 4) >,
+			< 1804800 MHZ_TO_MBPS(1555, 4) >;
 	};
 
 	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
@@ -3420,9 +3429,9 @@
 		qcom,cpulist = <&CPU6 &CPU7>;
 		qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
 		qcom,core-dev-table =
-			< 1267200 MHZ_TO_MBPS( 547, 4) >,
-			< 1555200 MHZ_TO_MBPS( 768, 4) >,
-			< 1708800 MHZ_TO_MBPS(1017, 4) >,
+			< 1267200 MHZ_TO_MBPS( 768, 4) >,
+			< 1555200 MHZ_TO_MBPS(1017, 4) >,
+			< 1708800 MHZ_TO_MBPS(1353, 4) >,
 			< 1900800 MHZ_TO_MBPS(1555, 4) >,
 			< 2208000 MHZ_TO_MBPS(1804, 4) >,
 			< 2400000 MHZ_TO_MBPS(2133, 4) >;
@@ -3967,8 +3976,8 @@
 
 			qcom,speed-bin = <159>;
 
-			qcom,initial-pwrlevel = <5>;
-			qcom,ca-target-pwrlevel = <4>;
+			qcom,initial-pwrlevel = <6>;
+			qcom,ca-target-pwrlevel = <5>;
 
 			/* NOM_L1 */
 			qcom,gpu-pwrlevel@0 {
@@ -4024,9 +4033,18 @@
 				qcom,bus-max = <7>;
 			};
 
-			/* XO */
+			/* MIN SVS */
 			qcom,gpu-pwrlevel@6 {
 				reg = <6>;
+				qcom,gpu-freq = <180000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <5>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <0>;
 				qcom,bus-freq = <0>;
 				qcom,bus-min = <0>;
@@ -4126,7 +4144,7 @@
 &pm6150_vadc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&usbcon_tem1_default &usbcon_tem3_default>;
-	
+
 	smb1390_therm {
 		reg = <ADC_AMUX_THM2>;
 		label = "smb1390_therm";
@@ -4162,7 +4180,7 @@
 			bias-high-impedance;
 		};
 	};
-	
+
 	usbcon_tem3 {
 		usbcon_tem3_default: usbcon_tem3_default {
 			pins = "gpio8";
@@ -4259,7 +4277,7 @@
 		qcom,hw-settle-time = <200>;
 		qcom,pre-scaling = <1 1>;
 	};
-	
+
 
 //#ifdef OPLUS_FEATURE_CHG_BASIC
 // add by longchangsheng for little board ntc
@@ -4269,7 +4287,7 @@
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 		qcom,pre-scaling = <1 1>;
-	}; 
+	};
 //#endif
 };
 
@@ -4280,7 +4298,7 @@
 			bias-high-impedance;
 		};
 	};
-	
+
 	batt_therm {
 		batt_therm_default: batt_therm_default {
 			pins = "gpio10";
diff --git a/arch/arm64/boot/dts/20711/sdmmagpie-gpu.dtsi b/arch/arm64/boot/dts/20711/sdmmagpie-gpu.dtsi
index f07018b9d798..8293bdf2fb1c 100644
--- a/arch/arm64/boot/dts/20711/sdmmagpie-gpu.dtsi
+++ b/arch/arm64/boot/dts/20711/sdmmagpie-gpu.dtsi
@@ -68,7 +68,6 @@
 
 		/* <HZ/12> */
 		qcom,idle-timeout = <80>;
-		qcom,no-nap;
 
 		qcom,highest-bank-bit = <14>;